Many past efforts have attempted to minimize the elements required to produce a particular logic function. Successful efforts were characterized by using a minimum number of logic gates. Also, efforts have been made to produce logic gates which require a minimum number of basic switching elements and a minimum chip area on an integrated circuit.
The present invention is directed towards optimizing both of the above desires. The number of logic gates and the number of switching elements are simultaneously minimized in cases where similar logic outputs are required. Wasteful duplication of logic gates and switching elements is prevented in those cases where the separate optimization of the number of logic gates required and the number of switching elements required for each logic gate do not result in the optimum solution for a particular circuit, i.e., the minimum number of switching elements in the entire circuit. This is most often true in Large Scale Integration (LSI).